Replies to post #28956 on Advanced Micro Devices Inc (AMD)

[Petz]

Hash Table addressing of huge datasets is suicide for long memory pipeline (P4-like) architectures. The addresses, even for similar sets of data, will result in random addresses, not likely to be in a cache, unless the entire hash table fits in the cache. So low memory latency, as provided by on-board memory controller, is exactly the right prescription to speed up access to hash-table-addressed data.

Petz