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SemiconEng

02/13/04 12:13 AM

#8972 RE: Elmer Phud #8970

SI's preliminary analysis has confirmed the presence of seven levels of copper metalization and revealed several industry firsts, including an advanced nickel - silicide process on the transistor gates, a strained silicon SiGe layer to improve channel mobility, and uniquely customized PMOS and NMOS devices. The process also confirms Intel's stated position that SOI is unnecessary to achieve high performance.


I notice the Layer descriptions seem very detailed. I had read somewhere else, that intel had worked on nickel salicide way back when, but never got it working. Appears they finally did. Also, Sounds like SI got their hands on a Prescott and either did a cross sectional analysis, or peeled back the layers. 7 Layer metal huh? Up 1 from 0.13u. I Wonder what sort of speed path improvement would be achieved if they added additional Metal Layers, vs. the additional defect issue. Think it would be worth it to go for 8 layer?

Semi
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wbmw

02/13/04 12:17 AM

#8973 RE: Elmer Phud #8970

Elmer, Re: SI's preliminary analysis has confirmed the presence of seven levels of copper metalization and revealed several industry firsts, including an advanced nickel - silicide process on the transistor gates, a strained silicon SiGe layer to improve channel mobility, and uniquely customized PMOS and NMOS devices. The process also confirms Intel's stated position that SOI is unnecessary to achieve high performance.

And in spite of all this - not to mention the much deeper pipeline - Prescott still fails to reach the same clock frequency as Northwood. I still think the engineers should hang their heads in shame.

Of course, things are bound to get better, but when?