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tecate

08/15/07 3:49 PM

#82009 RE: mas #82005

I think you must be hanging out in the chuckieD school of AMD PR bullshit believers club. are you asking for us to 'believe you' based on what?
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chipguy

08/15/07 3:49 PM

#82010 RE: mas #82005

The design was characterised as a 2.8 GHz device at 95W at ISCCC2007

The clock distribution system in Prescott was designed to
operate at up to 4.5 GHz according to an ISSCC paper.
Things didn't quite work out that way.

3.2-3.4 GHz is very likely in 2008

Sure and 30 MB of ZRAM has 1 ns access time too.
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wbmw

08/15/07 3:58 PM

#82015 RE: mas #82005

Re: Don't mistake initial speedpath glitches for poor long-term potential. The design was characterised as a 2.8 GHz device at 95W at ISCCC2007 and with split-power motherboards 3.2-3.4 GHz is very likely in 2008.

Looks like you've had a peek at AMD's internal roadmaps. Quite optimistic, I would say. Maybe they should concentrate on getting that 3.0GHz demo productizable before looking ahead of that. Of course, I don't think Intel will be standing still while AMD tries to catch up.