You're probably right about the RDRAM vendors, I wouldn't know, but the chipset guys have a different approach. The production trend for highspeed interfaces is to not test it directly to spec (too expensive) but instead demonstrate that it is free of defects at speed. This can be done effectively with BIST and without going off die. I would be very surprised is AMD wasn't doing the same thing with Hammer's HT interface on old ATE.
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