Actually, unlike OUM and traditional flash, the number of read/writes cycles on MRAM is supposed to be in the 10^17, essentially life of the system. But I agree with you, MRAM could definitely take a good chunk of flash in embedded systems, even in removable memory media. The problems are very high cost and not yet amenable to the 100 nanometer technology now being implemented with DRAM. NVEC solved the basic hurdle of cross talk, but I don't think that they have ever built (or CY built) anything under .5 microns cells. It is also a major problem to deposit and control the very thin tunneling barrier between the two magnetic layers. That barrier is just 15 angstrom or so (about 3 to 4 lattice distances or three to four atomic depth) and because subsequent deposition involve some temperature and annealing, diffusion of iron , nickel and cobalt into the very thin aluminum oxide tunneling barriers is probably going to cause extreme problems. Other tunneling barriers in silicon based devices are made of silicon oxide, thus such problems are avoided (the oxides of Fe, Ni and Co are all polaronic conductors, and in very thin layers probably excellent conductors, due to loss of polarization, and thus not suitable for tunneling barriers), and even then, a major source of low yields involves the difficulty in controlling correctly such a very thin insulating layer. IFX is trying to use Hafnium oxide for the tunneling barrier (a more refractory oxide than sapphire) and I wish them well, they are busy peeling the onion. There exist is such a simple solution, but unless they call me (US Patent 5,064,809), they'll be busy peeling that onion (g).
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