Re: pipeline's front-end instruction fetch and decode logic id refined to deliver a greater degree of instruction packing from the decoders to the execution pipe schedulers
If that's all you found, I don't think it does the improvements any justice. AMD added a couple of additional pipeline stages to accommodate the vastly different front end design, and the improvements to the SSE engine aren't even mentioned there. I'll agree the TLB improvements probably add 0-5% to performance overall, which goes towards explaining some of the improvement, but you may want to look at this article for a deeper appreciation of what went into the K8 design.
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