Intel Corp (INTC)

[Andy Grave]

Double patterning starts at the 20nm for TSMC according to my googling...


thanks.....I was not aware of this.....apparently they used double patterning at 28nm but not for splitting pitch in half but just for simply cutting the edges of patterned lines.....this according to Burn Lin (Vice President, Research & Development, TSMC).........Lin is a first rate technologist.....world renown......he was at Watson labs when I was there in the early 80s.....totally non political.....just did his thing....and very very well.


Interview: TSMC VP on Roadmap for Lithography Technologies

Jul 2, 2013 16:24 Masahide Kimura, Nikkei BP Semiconductor Research


Burn J. Lin, Vice President, Research & Development, TSMC

Nikkei BP Semiconductor Research interviewed Burn J. Lin, Vice President, Research & Development, TSMC (Taiwan Semiconductor Manufacturing Co Ltd), on the roadmap for the company's lithography technologies.

As the development of EUV (extreme ultraviolet) lithography technology is lagging behind schedule in the entire industry, TSMC will continue to use its ArF immersion lithography, which the company introduced for the 40nm process, for 28, 20, 16 and 10nm processes.

While TSMC has been using single lithography based on ArF immersion for the 28nm and older processes, it will introduce a double-patterning technology, which splits the pattern pitch formed in the first lithography in half, for the 20nm process.

TSMC has been using a method to form patterns by applying lithography twice in the aim of, for example, cutting the edges of patterned lines. But Lin said, "For the 20nm process, we started to use it in the aim of splitting pitch in half for the first time." The company started trial production with the 20nm process technology in 2013.

For the 16nm process, with which TSMC will start trial production in 2014, the company will introduce a FinFET technology using a 3D channel structure. Therefore, the power consumption and performance of chip will be improved.

However, TSMC basically will not change the design rules for metal wiring. So, the density (pitch) of circuit pattern with the 16nm technology will be equivalent to that with the 20nm technology. In other words, the company will not make major changes to the lithography technology. Still, Lin said, "We need to make improvements to the lithography technology to cope with the 3D structure of the FinFET."

For the 10nm process, with which TSMC will start trial production in the second half of 2015 to the first half of 2016, the company will introduce a quadruple patterning technology, which will narrow pitch to 1/4, for some critical layers while using ArF immersion.

Also, TSMC plans to employ its EUV lithography technology for some layers in the 10nm or 7nm generation if technology development proceeds smoothly. The schedule for the trial production with the 7nm process has not been determined yet. But it is expected to start in 2018 according to Moore's Law.