Advanced Micro Devices Inc (AMD)

[alan81]

I think the issue is floating point,
And in particular linpack. I think the fused macro-ops will allow four floating point operations per cycle, bringing floating point performance above the P4... when code is compiled to take advantage of the "virtual FMAC".

Personally, I am not convinced either Athlon 64 NOR conroe will be constrained to 3.2Ghz in 2006. 3.2 is pretty safe, but I think there is an outside chance 65nm will push Athlon 64 above that... and there is a chance the deeper pipeline on Conroe will push it above that.
--Alan