Sunday, December 04, 2005 5:38:31 PM
One would assume there would be 1MB parts at the high-end at least. You do know that AMD's clock per power is going up all the time, here's a clue, in Isscc 2006 AMD are presenting a paper on a 95W 2.6 GHz dual-core demonstrating pacifica which means it almost certainly already exists in silicon.
p26
http://www.isscc.org/isscc/2006/ap/2006_AP_Final.pdf
"
5.4 A 2.6GHz Dual-Core 64b x86 Microprocessor with DDR2 Memory
Support
3:15 PM
M. Golden1, S. Arekapudi1, G. Dabney2, M. Haertel1, S. Hale1,
L. Herlinger2, Y. Kim2, K. McGrath1, V. Palisetti1, M. Singh2
1Advanced Micro Devices, Sunnyvale, CA
2Advanced Micro Devices, Austin, TX
A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-Vt partially-depleted SOI process with 9 layers of
copper interconnect. The chip achieves a clock frequency of 2.6GHz at 1.35V while dissipating 95W.
"
Triple-Vt sounds like different voltage planes to me too which would be a whole new ballgame at lower clock levels.
p26
http://www.isscc.org/isscc/2006/ap/2006_AP_Final.pdf
"
5.4 A 2.6GHz Dual-Core 64b x86 Microprocessor with DDR2 Memory
Support
3:15 PM
M. Golden1, S. Arekapudi1, G. Dabney2, M. Haertel1, S. Hale1,
L. Herlinger2, Y. Kim2, K. McGrath1, V. Palisetti1, M. Singh2
1Advanced Micro Devices, Sunnyvale, CA
2Advanced Micro Devices, Austin, TX
A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-Vt partially-depleted SOI process with 9 layers of
copper interconnect. The chip achieves a clock frequency of 2.6GHz at 1.35V while dissipating 95W.
"
Triple-Vt sounds like different voltage planes to me too which would be a whole new ballgame at lower clock levels.
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