Rambus (RMBS)

[calbiker]

Rambus must now choose 10 claims to take to trial from the pool of 50, which includes the 29 claims in which the judge has already found patent infringement by the Korean chipmaker.

Those 10 claims are now chosen.

http://investor.rambus.com/downloads/2005-01-21%20Rambus%20Election%20of%2010%20Claims%20for%20Trial...

Can't say I understand Rambus' choices.

5,915,105

34. The memory device of claim 31 further including clock receiver circuitry to receive the first external clock and wherein the internal clock generation circuitry includes delay locked loop circuitry, coupled to the clock receiver circuitry, to generate the first internal clock signal and the second internal clock signal using at least the first external clock.

6,034,918

24. The method of claim 18 further including storing a delay time code in an access time register, the delay time code being representative of a number of clock cycles to transpire before data is output onto the bus after receipt of a read request and wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time code.

33. The method of claim 18 further including generating at least one internal clock signal using a delay locked loop and the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.

6,324,120

33. The memory device of claim 29 wherein the first operation code includes precharge information.

6,378,020

32. The integrated circuit device of claim 31 wherein the input receiver circuitry receives address information synchronously with respect to the external clock signal.

36. The integrated circuit device of claim 35 wherein the clock alignment circuit generates an internal clock signal, and the output driver circuitry outputs data in response to the internal clock signal.

6,426,916

9. The method of claim 1 wherein the first operation code includes precharge information.

28. The memory device of claim 26 wherein in response to a second operation code, the value is stored in the register.

40. The memory device of claim 26 further including delay lock loop circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal, wherein the plurality of output drivers output the amount of data in response to the internal clock signal.

6,452,863

16. The method of claim 15 wherein the first amount of data is sampled over a plurality of clock cycles of the external clock signal.