neye_eve: I agree. Maybe AMD will use IBM's experience to increase cache density in later cores.
But AMD (together with MOT) already presented a 1.33 um² SRAM cell for the 90nm node and IIRC also a 2.48 um² cell for 130nm. I wonder what keeps them from using it? Currently it seems they use a 4 um² cell for 130nm.
(for comparison: Intel's 130nm cell is 2.09 um², their 90nm cell is 1 um²)
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