Advanced Micro Devices Inc (AMD)

[DDB]

wmbw - ok, let's go the SRAM cell size way:
Intel's smallest SRAM cell in 130nm has an area of 2.09um². If we take 9 bit per stored byte:
2^20*9*6 = 56.6 mill. transistors.
56.6 mill. T divided by 2.09 um²/T = 27 mm²
+15% for tags, some logic and redundancy = 31 mm²

83 mm² + 31 mm² = 114 mm²

The linked image was meant for visual comparison of feature sizes (to identify possibly enlarged areas). I did my measurement long time ago using http://www.sandpile.org/impl/pics/intel/pm/die_013.jpg

You and I know, that the size of this die is 83 mm². Both are we able to find the L2 cache on this picture. So the simplest task (which even works if the image would have been stretched in some direction) is to calculate the relation of L2 area to the whole die, use this to get the L2 area in mm² and add that to the known size. Done.

So the real area of 1MB L2 should be very close to 32 mm², which means more than twice the density of AMDs caches (K7/K8).