Advanced Micro Devices Inc (AMD)

[chipguy]

I wonder if the high density of Intel cache is part of their heat problem.

Umm no. L2/L3 cache is the coolest thing on an MPU other
than decoupling caps and company logos.

Here's a clue from a paper presented at GLVLSI '02. The
1.75 MB integrated L2 cache in the Alpha EV7 covers 37%
of the die area and includes 85% of the transistors but it
accounts for only 7% of chip power.

I recall that when AMD implemented a high density cache on 130nm they initially had a problem with hot spots and had to back off their aggressive density goals.

Either AMD was utterly incompetent in their effort or you
recall wrong. I lean to the latter explanation.