could be right... I was going off my historical observations from my work on flash memory, but after some thought I guess on a uP you would not expect it to go down much. What I was thinking is that the FET's get much weaker, which should result in lower power... but in a full CMOS clocked circuit that will not happen. I suspect in the SRAM sense amplifiers, and any dynamic logic you would see a drop in power though... but that should be very small compared to the CVF power... and would appear as part of the "leakage" power. Thanks for the clarification. --Alan
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