AI
Wednesday, March 31, 2004 8:00:49 PM
Keith,
Hmmm, this may be the reason why we´re discussing it, exactly this aspect
I replied before reading what was ahead in the thread. The issue was discussed, and by the time I got to my reply, it was too late to edit or delete.
BTW, the discussion kind of died down. Do you have any ideas about this seeming discrepancy?
One explanation would be that AMD figured out the problems with oversized SRAM cell size, and the new cell size (and resulting L2) is tiny.
But it just creates more questions. The rest of the CPU then shrunk by a much smaller ratio.
Also, why would there be all this talk of Winchester with reduced L2 (and even Paris follow on) if AMD could instead be doubling the size of the cache for the premium chips, and leaving it at 1 MB for the rest of the lineup. If 1 MB is 24 mm^2 and 2 MB 48 mm^2, it would seem to me that AMD should be fine with just those 2 cores.
I think one piece of the information (102 mm^2 dor 512KB and 114 mm^2 for 1MB L2) is wrong.
Joe
Hmmm, this may be the reason why we´re discussing it, exactly this aspect
I replied before reading what was ahead in the thread. The issue was discussed, and by the time I got to my reply, it was too late to edit or delete.
BTW, the discussion kind of died down. Do you have any ideas about this seeming discrepancy?
One explanation would be that AMD figured out the problems with oversized SRAM cell size, and the new cell size (and resulting L2) is tiny.
But it just creates more questions. The rest of the CPU then shrunk by a much smaller ratio.
Also, why would there be all this talk of Winchester with reduced L2 (and even Paris follow on) if AMD could instead be doubling the size of the cache for the premium chips, and leaving it at 1 MB for the rest of the lineup. If 1 MB is 24 mm^2 and 2 MB 48 mm^2, it would seem to me that AMD should be fine with just those 2 cores.
I think one piece of the information (102 mm^2 dor 512KB and 114 mm^2 for 1MB L2) is wrong.
Joe
