Wednesday, February 20, 2008 2:19:39 PM
There was a database forum in Boston a few weeks ago and I think that it was put together by Stonebraker and MIT. Stonebraker is pushing his relatively new company, Vertica as a replacement for the mainstream database vendors and talking up how hardware changes have made the mainstream vendors obsolete.
Someone from Google gave a presentation on Map Reduce and I think that there were negative comments made on it by someone associated with Stonebraker. The printed version is floating around somewhere.
One of the attendees gave me a paper on the latest bottleneck (I think that it was from CMU) in L2 cache. It said that L2 cache has gone way up (they used the Itanium and 16 mb cache in Xeons as examples - I didn't know Xeon caches were that big now). The paper was pushing an approach to databases called staged processing as a new database paradigm. They didn't actually come up with anything but it was just a suggested area for future research. They mentioned that L2 cache latencies were much lower than they are today. It also discussed Sun's approach and liked the approach though you don't have current mainstream vendors that provide the software to try to take advantage of the architecture. Do you agree on the latency vs size issue? And is it a problem in the real world?
One other thing is that I spoke to one of the attendees and he has a Phd in CS and he thought that we were coming to the end of significant performance improvements in CPUs. I just thought about Intel's roadmap and disagreed and provided a few examples. So I may have changed his opinion on hitting the limits on hardware. He had a friend at a chip company that talked about the frequency/power limits that they had hit with their chips. So I just told him about HK/MG and overclockers hitting 4.0 Ghz routinely with Wolfdale. It seems to me that there's still quite a bit in Intel's hardware pipeline - do you concur?
Someone from Google gave a presentation on Map Reduce and I think that there were negative comments made on it by someone associated with Stonebraker. The printed version is floating around somewhere.
One of the attendees gave me a paper on the latest bottleneck (I think that it was from CMU) in L2 cache. It said that L2 cache has gone way up (they used the Itanium and 16 mb cache in Xeons as examples - I didn't know Xeon caches were that big now). The paper was pushing an approach to databases called staged processing as a new database paradigm. They didn't actually come up with anything but it was just a suggested area for future research. They mentioned that L2 cache latencies were much lower than they are today. It also discussed Sun's approach and liked the approach though you don't have current mainstream vendors that provide the software to try to take advantage of the architecture. Do you agree on the latency vs size issue? And is it a problem in the real world?
One other thing is that I spoke to one of the attendees and he has a Phd in CS and he thought that we were coming to the end of significant performance improvements in CPUs. I just thought about Intel's roadmap and disagreed and provided a few examples. So I may have changed his opinion on hitting the limits on hardware. He had a friend at a chip company that talked about the frequency/power limits that they had hit with their chips. So I just told him about HK/MG and overclockers hitting 4.0 Ghz routinely with Wolfdale. It seems to me that there's still quite a bit in Intel's hardware pipeline - do you concur?
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