Tuesday, January 29, 2008 12:04:06 PM
The bulk of HPC purchases has evolved into clusters of 2s
nodes, a configuration which is right in the middle of the
x86 SHV server heartland. Expecting IPF based 2s systems
to beat x86 in performance/price with a process lag is IMO
absurd. What will happen when both Xeon and IPF are at 32
nm at nearly the same time? I'm pretty damn sure the IPF
chip will easily beat the best x86 chip in absolute FP/HPC
performance but I am also pretty damn sure that the IPF
chip will be priced 2x to 5x higher than Xeon DP because
of its greater system scalability and RAS features. If Intel's
IPF division wants to take a greater share of the HPC cluster
market it will have to figure out a way to defeature IPF MPUs
for SKUs that are still superior to x86 for 2s HPC nodes and
sell them at comparable prices to Xeon DP but defeatured
enough to keep them out of 4s+ systems and commercial
servers which will be targeted by much higher priced SKUs
which is IPF's raison d'etre.
nodes, a configuration which is right in the middle of the
x86 SHV server heartland. Expecting IPF based 2s systems
to beat x86 in performance/price with a process lag is IMO
absurd. What will happen when both Xeon and IPF are at 32
nm at nearly the same time? I'm pretty damn sure the IPF
chip will easily beat the best x86 chip in absolute FP/HPC
performance but I am also pretty damn sure that the IPF
chip will be priced 2x to 5x higher than Xeon DP because
of its greater system scalability and RAS features. If Intel's
IPF division wants to take a greater share of the HPC cluster
market it will have to figure out a way to defeature IPF MPUs
for SKUs that are still superior to x86 for 2s HPC nodes and
sell them at comparable prices to Xeon DP but defeatured
enough to keep them out of 4s+ systems and commercial
servers which will be targeted by much higher priced SKUs
which is IPF's raison d'etre.
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