Intel Corp (INTC)

[chipguy]

I think it's an alignment thing, not a thickness thing. Intel described going to "gate last" rather than "gate first" and this has raised speculation about gate alignment and TPTs.

Back to the future. Gate alignment was a big issue with metal
gate CMOS in the 1970s. If the gate shifted and overlapped
the source or drain region a significant parasitic capacitance
was formed that was also effectively magnified by the Miller
effect. That is why self-aligned poly gate processes was such
a big breakthrough in those days.

I doubt gate misalignment will be as important to performance
variation today because at current feature sizes and beyond
interconnect capacitance tends to overwhelmingly dominate
critical timing paths in high end MPUs.