There was much speculation about essentially the same thing on Intel's 65nm process. One website was saying that because of Intel's almost perfectly aligned gates they must have a lot of failing die that couldn't meet that perfect alignment. I'm not a process guy and I'm probably doing a poor job of describing this but that's the essence of it. It wasn't true but it sure sounded like it should be true. Now the same argument is cropping up again with your's and other's speculation about some of the details of the 45nm MG process not being self aligning. Gate first vrs gate last. It was described in one of Intel's papers. Time will tell if this is a real issue or a non issue like 65nm.
Market Data 
Markets 
AI
