Thanks for the pointer, Saturn.
Since Intel hasn't commented on the Nehalem floorplan at all yet, then I think it's probably inappropriate to comment further. I will say you are right to be skeptical; there are inaccuracies there in Hans' analysis (more like guess, I think).
To address one of your guesses at an error, I can say that I am honestly not sure if the L2 cache is inside or outside the core. So I will speculate there. You will notice that Hans says the core size has increased in size from 22 mm2 to 29.6 mm2. It seems more logical to me that this is due to the L2 being inside the core. But like I said, I don't know that for sure.
My little teaser comment about there being "clues" in the floorplan was meant to be taken at a very high level, and point out the significance of lining up the cores in a row like this. What I always thought was interesting was how many boxes you could draw around various subsets of that die, and have all the necessary ingredients for a product in a particular market segment. I don't think that Intel is throwing around the term 'scalability' as just an empty buzzword these days...
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