Intel's X86 response to the mobile market may use 20% of the power of their current generation due out in Q1 2008, but what many of your are forgetting is that it will be built on a 32nm process. This alone is responsible for much of the power savings, performance increases and size constraints. Assuming that electrical leakage doesn't increase and that they don't dramatically up the transistor count, the die shrink alone will result in 1/8 the silicon being used over the 65 nm technology. This is just an estimate taking into account the diminished trace sizes, and assuming everything scales which it won't quite scale linearly because insulation between the trace will still have to be a certain thickness.
Even if they add transistors (up the amount of L1/L2 cache and everything doesn't scale linearly like in the past), then at the very most the chips will be 25% the size and use 25% the power. So those power figures aren't that impressive. MRVL is just starting to use 65nm with Tavor and TSMC's 65nm capability. I still think that ARM processors on a 32nm process will be more than competitive with Intel's offerings. To get more of an idea for how much of an impact die shrinks have on ARM processors, I think looking at the chips built at the 200 mm plant in Colorado and comparing them to TSMC's might shed some light on MRVL's ability to reduce costs and lower power consumption.
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