Saturday, January 24, 2004 2:08:37 PM
Elmer, I mean a little of both. First, you get less die per wafer just because of the size, other things being equal.
Second, you have a greater probability of failure for a particular die because of the much greater number of transistors and larger area. Yes, you can mitigate that by putting redundancy in the cache. This will protect against single bit failures. You still get larger failures due to imperfections in the silicon substrate or slips in the surface due to the difficulties in annealing a large wafer evenly. With a smaller die, the odds are better that a particular die will fit between these imperfections. A illustrative simplification: N imperfections of a given size will destroy a constant N number of die, no matter how many die per wafer can be cut. So, the more die you can cut from the wafer, the higher the yield after this particular type of problem.
Also, Itanium has a larger core with more transistors than P4 or Opteron at the same geometry, as I understand it. Bit failures in the core present more difficulties than bit failures in cache (harder to design redundancy in the core). The randomness of these failures for a given gate design and process predict more failed cores for the one with more transistors.
I think that Intel is dealing with these issues by refining the process on existing technologies so that they can reduce the defect rate (by implementing on older, established process). This means a lot of extra engineering time (and expense) to get things working at an accepable level. Also, they can tolerate a lower yield because Itanium enjoys a higher ASP than P4.
Eventually, for Itanium to be a mass market product, it will have to be implemented in a timely manner on the newest process. With a design that always calls for much more transistors, this will be an interesting challenge.
If that's your claim then I'd challenge you to support that with something more than speculation.
We are all speculating based on what is reasonable, because Intel isn't about to show their hand. It would be nice if we could base our arguments on all the details, but life sometimes isn't that clean.
Second, you have a greater probability of failure for a particular die because of the much greater number of transistors and larger area. Yes, you can mitigate that by putting redundancy in the cache. This will protect against single bit failures. You still get larger failures due to imperfections in the silicon substrate or slips in the surface due to the difficulties in annealing a large wafer evenly. With a smaller die, the odds are better that a particular die will fit between these imperfections. A illustrative simplification: N imperfections of a given size will destroy a constant N number of die, no matter how many die per wafer can be cut. So, the more die you can cut from the wafer, the higher the yield after this particular type of problem.
Also, Itanium has a larger core with more transistors than P4 or Opteron at the same geometry, as I understand it. Bit failures in the core present more difficulties than bit failures in cache (harder to design redundancy in the core). The randomness of these failures for a given gate design and process predict more failed cores for the one with more transistors.
I think that Intel is dealing with these issues by refining the process on existing technologies so that they can reduce the defect rate (by implementing on older, established process). This means a lot of extra engineering time (and expense) to get things working at an accepable level. Also, they can tolerate a lower yield because Itanium enjoys a higher ASP than P4.
Eventually, for Itanium to be a mass market product, it will have to be implemented in a timely manner on the newest process. With a design that always calls for much more transistors, this will be an interesting challenge.
If that's your claim then I'd challenge you to support that with something more than speculation.
We are all speculating based on what is reasonable, because Intel isn't about to show their hand. It would be nice if we could base our arguments on all the details, but life sometimes isn't that clean.
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