Advanced Micro Devices Inc (AMD)

[HailMary]

To execute an x86 instruction takes a certain amount of
logic gate wiggling. Regardless of whether a given level
of performance is obtained by wiggling many logic gates
relatively slowly or fewer gates faster, the amount of
power consumed won't vary greatly for a given process
feature size and supply voltage.

I'm surprised by your post, chipguy. That is way oversimplified. Architectures themselves can be high or low power oriented based on their efficiency and amount of speculative execution they do. It is all about tradeoffs. You can add an architecture feature that might buy you 2% in benchmarks, but adds 5% in power consumption. The project planners have to decide what is more important. It is all about making wise choices early on.

Also - the physical design itself can be optimized for power. I would guess Intel has the upper hand here as they have lots of resources to throw at this.