Intel Corp (INTC)

[Elmer Phud]

wbmw -

http://www.chip-architect.com/news/2007_02_19_Various_Images.html

On Hans' chart when he has die area, core and cache size, he has Penryn at 107mm2 for the die. There's 44mm2 for the core (22mm2*2) and 36mm2 for the cache (6mm2*6).

So 44mm2 + 36mm2 = 80mm2. What's the other 27mm2 for?



What am I missing here? Am I reading this chart wrong?