Intel Corp (INTC)

[wbmw]

Justaview, are you familiar with victim caches? AMD claims that their L3 uses this policy. From what I have seen, these are easier to design, since the L2s simply write back to the L3 instead of memory, but they really don't improve locality all that much. All a victim cache contains is the LRU or least recently used data that has not been accessed for a while in the L2. AMD's L2 caches have traditionally been 16-way set associative, so if there are 16 more recent copies of data per set in the L2, I can't imagine they'll hit the L3 very often. Alternatively, they could have doubled their L2 and made it 32-way set associative, but this probably would have increased the latency of the decode and lowered performance. Instead, they have essentially doubled their cache size, but half of it resides much farther away from the CPU. Is it a net win? I'm sure AMD's architects have found workloads where it helps a little, but I can't imagine there are many of them where it helps a lot.