Intel Corp (INTC)

[Tenchu]

Elmer, > But if the cache is shared there is no snoop.

I see what you mean now. I thought you were referring to external snoops, i.e. from the bus.

I think it doesn't make a difference for Barcelona. The L2s might be separate, but the L3 is shared. And I'll bet the policy between the L2 and L3 is write-through. In other words, if it isn't in the L3, it isn't in any of the L2s. That way, one core doesn't have to probe the other cores on a local L2 miss.

Tenchu