Intel Corp (INTC)

[Wouter Tinus]

Even the basic assumtion of his calculation appears to be false, because according to this article* the L1I-cache bus is "160+ bits" (so over 20 bytes) wide. Is there a more definitive number in the public domain?

* http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144&p=4

That article also puts the average instruction lenght at ~4 bytes instead of ~4.8 bytes. And there is a buffer in between the cache and the decoders that loosens the coupling between fetch bandwidth and decode rate.

Anyway, I just wanted to add some technical arguments to the discussion instead of just pointing and laughing ;)