NaS, Re: Give us a simple overview and comparison so we don't have to read 500 pages of technobabble to know where you are coming from.
If it's just technobabble to you, then maybe you don't have the knowledge to appreciate these kinds of features, even if I were to explain them in layman's terms.
Let me just put it this way: Newisys was on the right track, but their business model backfired, because their implementation was more expensive than what businesses were willing to pay for AMD based hardware. Let's face it, you can't win a reputation overnight, and people were unwilling to trust Newisys enough for them to recoup their R&D costs.
Now, putting those features into a solid system from one of the top OEMs, who can also abstract the processor enough that the buyer doesn't care who it came from, and then a Newisys level solution would be quite competitive. Although, OEMs were pretty reluctant to introduce platforms where they could not contribute to the features being integrated into the system. The Newisys model encouraged even the top OEMs to become nothing more than resellers. Doing so, however, would make them lose their only competitive strength against Dell, and that is the added robustness of an IBM or HP server system.
Of course, there is also another problem with AMD's architecture. A lot of the newer RAS features that you will find in systems over the next few years may not be possible using an AMD based system, since the features themselves are built into the memory controller of a new chipset.
Some of these features include memory mirroring, memory hotplug, hot add or subtract, memory RAID, memory sparing, or memory failover. AMD built in some basic chipkill functionality into their memory controller, which allows multiple ECC errors from a single x4 device to use the extra ECC pins to send data. AMD's implementation won't work for x8 or x16 devices, however, which are used in less expensive DIMMs.
In order to support these newer memory features, AMD must redesign their CPU core and add a lot of complex silicon that increases validation time to each new revision of the CPU. This would not be a big deal if Opteron were only a server chip, but AMD also wants to use it on the desktop and mobile, so if they want to implement complex designs they either need to manage a parallel design team for the server parts or delay their desktop and mobile introduction until they can finish implementing the more complex features.
Thus, the integrated memory controller becomes a double-edged sword, and it could hinder AMD from becoming RAS competitive in the future.
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