Re: Can you reference ANY document showing an "up to 20% gain" for any OTHER feature in the chip that is MORE applicable to the general case than low-latency memory access? I mean, you MIGHT have an argument re: SSE2 support, but that's hardly applicable to the "average" benchmark now, is it?
How about this. Instead of nitpicking one phrase out of one post, why don't you review the last dozen posts I've made and see if you can find a general theme. I don't mind accepting the fact that, of all the contributers of performance in a given app, the IMC may be the primary one from time to time. Instead, I am arguing against the myth that K8's performance relative to either previous generation K7 design, or even a Netburst design from Intel, is not so much the fact that it has the IMC, but rather that it has a very strong set of micro-architecture improvements that have raised the amount of instruction level parallelism extractable from normal code. These improvements have a greater affect than people give them credit for, and hard working AMD engineers spent a sizable amount of time working on this set of features. K8 is not just a strong performer because of its IMC, and it's not hard to match a K8 or even exceed it without one. It will be obvious to everyone very soon with Core 2 Duo that it's possible to increase the amount of ILP in an x86 processor to even exceed the benefit of an IMC by 20-40%. And it's not going to all be due to a large shared cache, either.
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