AI
Wednesday, May 10, 2006 2:24:33 PM
Re: You are really so funny if you believe the above fairy story 
. A little knowledge is a very dangerous thing . When you have a cache miss that data/instruction will experience the full memory latency regardless of whether it's pipelined with other cache misses. It can't pinch another previous oncoming memory request just because it's been requested earlier and the data it has may not be what it wants anyway. You are just too absurd for words.
Let me explain to you how pipelining can work for memory accesses.
Consider two cases. One is with no pipelining. You request 10 memory addresses that miss cache, and each one takes 70ns to complete. Since they are spaced apart, you can ignore DRAM bank conflicts. That's 700ns.
Now take a pipelined approach, where each transaction goes on the bus a few ns after the previous transaction. It still takes 70ns to return the first one. Assuming the others are headed to the same open bank, there should be no DRAM conflict, and the only delay would be the row and column access. If the memory addresses are sequential and in the same row, the latency is even smaller. For a 3 cycle CAS latency on a DDR400 module, you are looking at 15ns between activating the column strobe and getting the data return. Assuming dual channel memory, 64B of data takes 4 fast cycles to return, so that's another 10ns before another read can be issued. 70ns + 25ns * 9 transactions is 295ns, nearly a 60% improvement over the same 10 transactions unpipelined. And the more transactions, the more this number will grow. With faster and lower latency DRAM, the results are even better.
Of course, pipelining does not work if the transactions are spaced apart. So it depends on the workload and the pattern of memory access.
. A little knowledge is a very dangerous thing . When you have a cache miss that data/instruction will experience the full memory latency regardless of whether it's pipelined with other cache misses. It can't pinch another previous oncoming memory request just because it's been requested earlier and the data it has may not be what it wants anyway. You are just too absurd for words. Let me explain to you how pipelining can work for memory accesses.
Consider two cases. One is with no pipelining. You request 10 memory addresses that miss cache, and each one takes 70ns to complete. Since they are spaced apart, you can ignore DRAM bank conflicts. That's 700ns.
Now take a pipelined approach, where each transaction goes on the bus a few ns after the previous transaction. It still takes 70ns to return the first one. Assuming the others are headed to the same open bank, there should be no DRAM conflict, and the only delay would be the row and column access. If the memory addresses are sequential and in the same row, the latency is even smaller. For a 3 cycle CAS latency on a DDR400 module, you are looking at 15ns between activating the column strobe and getting the data return. Assuming dual channel memory, 64B of data takes 4 fast cycles to return, so that's another 10ns before another read can be issued. 70ns + 25ns * 9 transactions is 295ns, nearly a 60% improvement over the same 10 transactions unpipelined. And the more transactions, the more this number will grow. With faster and lower latency DRAM, the results are even better.
Of course, pipelining does not work if the transactions are spaced apart. So it depends on the workload and the pattern of memory access.
Discover What Traders Are Watching
Explore small cap ideas before they hit the headlines.
