AMD strictly moderated (AMD)

[mmoy]

It seems that this is a hotly debated issue in other places as
well.

http://www.aceshardware.com/forums/read_post.jsp?id=115161107&forumid=1

The article at http://arstechnica.com/wankerdesk/01q4/hammer/hammer.html
lists Hammer improvements as:

- General Purpose Registers (GPRs) extended out to 64 bits,
- Number of GPRs doubled from 8 to 16
- Number of SIMD (MMX, SSE, SSE2, and 3DNow!) registers doubled from 8 to 16
- Integrated DDR memory controller
- Integrated HyperTransport interface
- Improved branch prediction

The pipeline went from 10 to 12 stages.

I think that the benchmarks in this discussion centered around
32-bit benchmarks so the 64-bit stuff is not really applicable.
That leaves Improved branch prediction and increasing the
pipeline length. Were there any other microarchitectural
changes made? I imagine that Improved branch prediction
helps but this is already a short-pipeline machine.