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Wednesday, June 11, 2003 1:17:23 PM
chipguy, Too bad about that shared bus architecture eh?, LOL.
They had to price this system at $40K, probably this shared bus with two memory controllers was not so easy to make.
Let me give you the extract from rx5670 pdf: to support Itanium II potential, it is supported by high-bandwith (6.4 Gb/s) system nus and massive tertiary cache.
More: Proprietary system logic solutions are being developed to scale beiond 4 processors.
Nice, so HP added massive 4th-level cache and still claim they hit the ceiling of scalability without further improvements.
And you compare the cpu with 4 levels of cache with 2-level cache Opteron?
They spend those 40K to fight the limitations of Itanium shared bus, instead of adding some feature that are helpful for customers. Customer is always the last to cover Intel's bad design.
They had to price this system at $40K, probably this shared bus with two memory controllers was not so easy to make.
Let me give you the extract from rx5670 pdf: to support Itanium II potential, it is supported by high-bandwith (6.4 Gb/s) system nus and massive tertiary cache.
More: Proprietary system logic solutions are being developed to scale beiond 4 processors.
Nice, so HP added massive 4th-level cache and still claim they hit the ceiling of scalability without further improvements.
And you compare the cpu with 4 levels of cache with 2-level cache Opteron?
They spend those 40K to fight the limitations of Itanium shared bus, instead of adding some feature that are helpful for customers. Customer is always the last to cover Intel's bad design.
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