AMD strictly moderated (AMD)

[chipguy]

Um, you might want to take a look at a labeled K8 die photo before you embarrass yourself further.

You mean the annotated version of Wouter's photo on Ace's?

You have got to be joking. Compare the 90 nm and 65 nm die
photos. Notice the subtle differences in the small memory
arrays between the instruction pipeline and the datapath
side of the core.


You're clearly not looking very closely. It's *much* larger relative to the ALU, compared to the K8.

Maybe to the untrained eyes of someone who is hoping to see
something that is not there.


Yet another garbage post from you.

You really think the 65 nm K8's L2 is implemented with 8 rough
"row elements"?

http://www.aceshardware.com/forums/read_post.jsp?id=115160290&forumid=1

For an expert in producing garbage you sure can't tell what is
and isn't.