Replies to post #16423 on Advanced Micro Devices Inc (AMD)

[sgolds]

Tim, he is the first person I've seen claim that DDR-II will have higher latency than DDR-I. I do not accept this claim without a more authoritative explanation than that!

Second, P4 has a particular problem with latency: The long instruction prefetch queue has to get flushed and refilled whenever the branch speculation is wrong. Latency is particularly bad for this design. The P4 would perform a lot better if it put the memory controller on the die, like A64.

Thus I object on two grounds: He needs to show me that latency is a problem with DDR-II, and he needs to understand that this would hurt the P4 more.

[8-/]

Tim, What's your opinion?

Depends on where the latency is measured from.

What's the latency from CPU to chipset? One MOBO cycle or more?

What's the latency in the chipset? One MOBO cycle or more?

How often is cache refreshed from MM?

What's the overall latency between cpu looking in cache and getting data from Main Memory in each case, anyway?

It's too %#*& complicated for me to figure out. What's your best guess?

sgolds, What's your opinion, also as long as I'm wasting electrons?

8-/

[Jules2]

"Posted by: Tim Fowler
In reply to: sgolds who wrote msg# 16281 Date:10/31/2003 3:41:38 PM
Post #of 16448


I'm more interested in this part

"An interesting tidbit on the side is that Intel's P4 architecture, using all kinds of optimizations, including hardware-based dynamic speculative precomputing for branch-prediction and prefetching will be hurt less than AMD by the high latencies of DDR II. To spin this a bit further, the main advantage of AMD's Hammer architecture is the integration of the memory controller onto the CPU with the goal of reducing chipset-related (control and address decode) latencies. It only requires second grade math skills to see that shaving off one cycle out of nine (1/9) on the controller level for an initial access will yield less performance gain than reducing latencies by one cycle out of five (1/5) ."

What's your opinion?""

Tim.

I hope you will pardon me for jumping in here.
It's realy very simple, memmory performance is like oil & water. Bandwidth & Latency dont mix. Lets call bandwidth X, Latency Y. Performance z. Usable bandwidth = performance.
Thus, x-y=z.
This is why synthetic bench marks that measure but one aspect of the performance equasion dont mean squat.

Jules