Advanced Micro Devices Inc (AMD)

[sgolds]

Tim, he is the first person I've seen claim that DDR-II will have higher latency than DDR-I. I do not accept this claim without a more authoritative explanation than that!

Second, P4 has a particular problem with latency: The long instruction prefetch queue has to get flushed and refilled whenever the branch speculation is wrong. Latency is particularly bad for this design. The P4 would perform a lot better if it put the memory controller on the die, like A64.

Thus I object on two grounds: He needs to show me that latency is a problem with DDR-II, and he needs to understand that this would hurt the P4 more.