Second, P4 has a particular problem with latency: The long instruction prefetch queue has to get flushed and refilled whenever the branch speculation is wrong. Latency is particularly bad for this design. The P4 would perform a lot better if it put the memory controller on the die, like A64.
But with iHT another thread could still utilize the processor, thus overall throughput would not suffer as bad.
Second, P4 has a particular problem with latency: The long instruction prefetch queue has to get flushed and refilled whenever the branch speculation is wrong. Latency is particularly bad for this design. The P4 would perform a lot better if it put the memory controller on the die, like A64.
This is utter technobabble. It mixes up two completely distinct and independent factors of processor performance, branch misprediction penalty and sensitivity to memory latency.
sgolds, I'd put a good bit of stock in what MS(Michael Schuette) has to say about memory. He used to design for Mushkin(or the company that ate Mushkin(vice versa?)), if I'm not mistaken. He's very knowledgable about both memory and power circuitry, as you'll see if you read a few of his reviews. BTW, he has a great BIOS guide on his site (www.lostcircuits.com). Paul
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