Replies to post #13190 on Advanced Micro Devices Inc (AMD)

[Elmer Phud]

Chipguy -

But the HT channels probably can't be tested comprehensively
during wafer sort, only after packaging.

Actually they can't be tested parametrically at all. They can be characterized and guaranteed by design but actually testing them to spec would be impossible in a production environment. If you look at the specs and the accuracy of available test equipment you'll find that the guardbands turn out to be greater than the specs. Hold times would happen before setup times. It's a common problem with LVDS testing. RamBus was the same way (although not LVDS), as is USB 2.0, SATA and PCI-Express.

[kpf]

chipguy

Being unable to test before bonding out would make the whole concept of redundancy in chip-design obsolete.

I am pretty sure the K8-design allows using any of the three HTT-Channels for an Athlon64 or Opteron1xx and any two to make an Opteron 2xx. (Not only) AMD depends on the economies from such designs.

K.

[sgolds]

chipguy,

Presumably a one link Opteron has its one link on a specific set of pins. If it is kaput then having a working link on another set of pins, or perhaps not bonded out at all, isn't going to help.

Why?

Programable chips - reconfiguring the internal wiring by writing data to a programable port - is used in many applications. There are numerous ways to do this! It seems that to be able to design an internal HT to a logical block of pins, and then assign that logical block to physical pins by initializing from a port, should not be a hard spec.