Advanced Micro Devices Inc (AMD)

[chipguy]

Thanks lot for the explanations. As far as I understand there is some redundancy in the hypertransport channels: Only 8xx Opteron-models need every HTT-Channel to meet all specs.
If one channel does not meet all spec, its gonna be a 2xx-Opteron, if two do not meet specs its an 1xx or an Athlon64.
Parametric yield loss would only occur if all channels fail to meet specs - which hopefully is not a significant number.

But the HT channels probably can't be tested comprehensively
during wafer sort, only after packaging. Presumably a one link
Opteron has its one link on a specific set of pins. If it is
kaput then having a working link on another set of pins, or
perhaps not bonded out at all, isn't going to help.