InvestorsHub Logo
Followers 24
Posts 15456
Boards Moderated 0
Alias Born 12/30/2001

Re: chipguy post# 13190

Sunday, 09/14/2003 6:05:00 PM

Sunday, September 14, 2003 6:05:00 PM

Post# of 97585
Chipguy -

But the HT channels probably can't be tested comprehensively
during wafer sort, only after packaging.


Actually they can't be tested parametrically at all. They can be characterized and guaranteed by design but actually testing them to spec would be impossible in a production environment. If you look at the specs and the accuracy of available test equipment you'll find that the guardbands turn out to be greater than the specs. Hold times would happen before setup times. It's a common problem with LVDS testing. RamBus was the same way (although not LVDS), as is USB 2.0, SATA and PCI-Express.


Volume:
Day Range:
Bid:
Ask:
Last Trade Time:
Total Trades:
  • 1D
  • 1M
  • 3M
  • 6M
  • 1Y
  • 5Y
Recent AMD News