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Wuxi Becoming China's "Silicon Valley"?
Hynix inks contract for chip plant in Wuxi
http://www.digitimes.com/news/a20040818A4013.html
CSMC breaks ground for 8-inch fab in Wuxi
http://www.digitimes.com/news/a20040818A4014.html
Info on Wuxi China:
http://www.asiatravelling.net/china/wuxi/wuxi.htm
http://www.travelchinaguide.com/cityguides/jiangsu/wuxi/
http://reference.allrefer.com/encyclopedia/W/Wuxi.html
IF that is true, there are other considerations like market taste that would come into play, along with retail price demand sensitivity, that have nothing to do directly with the technology. [Although unit cost on a large scale does involve tech in the manufacture].
IDRK.
Right, but my point is, whatever the reasons, it's been reported that it is not a "technical issue" with the LCOS 1MPixel chip itself, simply intel misreading the market...... again. That's poor Management IMO, and it seems like all these type incidents started occuring during the current management's watch.
But it might be just my bias. I guess Craig's recent "finger pointing", towards the employees, still grates on me. IMO, if the Captain steers the ship towards the shallows, then the LEAST he should do is not try to blame it on the engine room if the ship gets stuck.
From MDR, good summary.
I don't know, I think this has just kept AMD alive. I don't think they have anything in the bag that they can pull out. Intel's response need only be "meets". And, you know it won't. The danger for AMD is that their future appears known. Whereas, Intel can reinvent. I can't believe that a full blown response is not coming... At worst, they keep the 20%, which, AFAICT, is fine with Intel.
Smooth
Maybe so, but I think intel needs to keep their eye on the ball, and not underestimate the market.
Example: Already, they've had to change direction, and delay the 1 M-Pixel LCOS TV chip, to the 2 M-Pixel because the market already has strong competition at 1M-Pixel, and intel is only now realizing this? What..... Nobody in Management saw that coming to begin with? Sheeesh, looks like another initial boner Management decision by Craig and company.
But hey, maybe he can try and blame that one on the employees too, eh?
Intel desktop price cuts slated for next week
http://www.theinquirer.net/?article=17935
CHIP GIANT Intel has scheduled the 22nd of August for the next round of price cuts on its desktop processors.
On that date there will be a whole range of price cuts on its LGA 775 and 478 pin Prescotts, as well as adjustments on its Celeron and Celeron "D" microprocessors.
Prices below are for quantities of 1,000. We don't know if you can get 1,000 Pentium 4 560s yet.
The price cuts are quite big. For example, the 560, launched in July at $637, will drop in price to $417.
There is nothing wrong with..... OK OK I'll give yall a break
I for one appreciated you taking the time to share your thoughts and experiences. I hope it continues.......
No longer interested in doing so, here. Thanks anyway.
Hey great minds think alike.
http://www.investorshub.com/boards/read_msg.asp?message_id=3829846
OK, I admit it, I stole it from you
But I agree about the "Great Minds" thing
Is it just me, or does anyone else see it as funny that if we rotate the last letter of AMD's CEO 90 degrees, Then he becomes Hector Ruin?
Not missing anything
Or worse, they could make them, but not in a cost competitive manner. They could alway just run more wafers but the cost would substantially increase. This would esplain also why they didn't lower the price to increase demand.
Also, you might not initially have an idea of what High Volume Yields would be. What looks good for Pilot runs, does not always translate once you ramp to higher volume. Since most likely, you wouldn't find that out until Metal-1 etest, even if you started additional wafers right then, the additional starts would be weeks behind the initial runs.
that's a shame as I hadn't finished reading all the links.
Too Bad. I thought it was enlightening, but since it was determined to be "unimportant semantics", I requested the deletion.
China Posts 21.6% Jump in PC Server Sales H1
http://tinyurl.com/5vfx5
PC servers based on Intel Architecture (IA) beat the traditional RISC (reduced instruction set computer) servers in sales growth for the Jan-June period. Inspired by strong sales, Intel unveiled Itanium 2, a high-end server CPU earlier in the month in Beijing.
An important point here is it took a year from "topping off" to "clean room ready", and then "silicon start" so clearly there are some tasks between the two
I think many here are very optimistic about how quickly this thing will go. I saw the same thing with posts regarding the UMC and AMD joint factory that is now, ummm, a UMC factory.
--Alan
I agree, way overly optimistic. I knew this as well as you did, from the start, but I was trying to use the public data, to get those people here to realize the over optimism by themselves. This is due, to what I've found, that historically, most of the time when I try to just tell people things around here, it is..... rarely received well, by some of the people here. In the past, my interest in this thread was far less then my desire to put up with the crap. Those have already been informed that they are ignored. So far, the rest, (not all), appear to be amazingly restrained this time. If not, I can always just go back to my own thread again. We'll see
Actually "Topping Off" ceremony takes place when the last structual member is being secured in place. The roof will not be started until that occures. Been involved in many of them! Every one of them had a "Press Release" at least in local newspapers. The big ones go regional or national.
Jules
Nit Piking aside (thanks so much, by the way)............ I believe "THE POINT" of my posting is still valid. Based on available information, The F30 and F36 top offs happened ~ in the same span of time, and in any case, IMO, basing estimates of Wafer starts on topping off is a mistake.
Fab 30 took (by Alan's rough timeline) 2-3 years from announcement to topping out - Fab 36 was announced in Dec 03 IIRC; the topping out ceremony was in May 04. So far they seem to be progressing significantly faster with Fab 36.
"Topping out" simply means putting the roof on the building, nothing more. This "accomplishment" (cough) does not usually even qualify for a Press Release. You can put a roof on a building anytime you want after the basic superstructure is completed. Topping out a building, says nothing about the condition of the cleanroom, and says noting about the estimated time to wafer start. It would be a mistake to extrapolate from that.
[edit] Especially since I just found Alan's estimates (while admittedly rough) may be off a little. His claim of topping off in in 1998 doesn't match with Hardware central's claim that the topping off was earlier.... in 1997. Maybe Alan just got his spacing incorrect? So, I wouldn't base my investments on "topping Off" information if it was me.
--------------------------------------------------------
Alan's estimate:
1997 - Cornerstone ceremony
Topping off ceremony
1998 - Clean room ready for equipment
---------------------------------------------------------
According To Hardware Central Interview
http://www.hardwarecentral.com/hardwarecentral/interviews/1920/1/
1996 - Ground breaking for facility
1997 - Cornerstone ceremony
Topping off ceremony
1998 - Clean room ready for equipment
"Yield"
Ed's Bolding......
http://www.overclockers.com/articles1085/
Digitimes has leaked some very interesting information about Hammer production (bolded print our emphasis):
Unit sales of Advanced Micro Devices (AMD) Athlon 64 (K8) processors are expected to grow 50% sequentially in the second half of this year, according to sources at Taiwan motherboard and chipset makers.
Improved yield rates for K8 processors and AMD’s recent price cuts, about 20% on average, for the Athlon 64 processor lineup, are two key factors driving second-half sales, stated the sources.
Unit sales of K8-based motherboards accounted for only about 5% of total motherboards sold in the first half because AMD was unable to improve the yield rate of the K8 processor, and the prices of the CPUs were relatively high, the sources said.
However, the sources noted that sales of K8 processors started gaining momentum in July and should continue to expand at a rapid pace in August, following the July 26 price cuts.
So now the truth comes out. AMD simply couldn't make a lot of Hammers.
Yes, I seem to remember something like that happening when fab30 was brought up. Was fab22 a "copy exact"? That would also help explain the speed with which the fab was brought up.
Yup, and get this, at the time, they sent several hundred engineers and technicians up there to Oregon to indoctrin...... ummmm I mean, get them copied exactly too. The idea was to transfer the "tribal knowledge", you know, the stuff "everyone knows", but nobody gets around to documenting? It worked very successfully. I remember reading somewhere that they are also sending a bunch of people from Fab12 up there while the conversion from 200-300mm is being done. Ah yes, here it is....
http://sanfrancisco.bizjournals.com/portland/stories/2004/04/19/daily26.html
Seems to me like copy exactly is continuing
I am sure things have changed quite a bit, but it is still not easy to bring up a new process, or even an old process in a new factory.
--Alan
New process bring up is a real PITA, that's for sure. Been there, done that. Not interested in doing it again
Well, there's a huge amount of stuff that needs to be done at fab36 once the walls and roof are up............
How fast it gets done, Depends on how much money you want to spend. The record Fab construction from greenfield site, to first wafer start, I believe, is currently held by intel Fab22, 18 months, with tons of money thrown at it. I wouldn't be surprised at double construction costs at that speed. Normal is 24-36 months.
Anyway, you don't actually have to have the Fab's outside walls up first. What actually happens, is that they put up the building's superstructure, and then build the internal cleanroom FIRST. Seal off the cleanroom, start pumping it down, clean it out, then slightly pressurize it, THEN you build the outside structure, put up the exterior walls, plumbing electrical, chemical, etc etc etc, and just "Hook Them Up", to the cleanroom equipment, through what's called "Pop Out's" in the Cleanroom sub floor, or ceiling.
Pretty cool huh?
When the process is brand new, you can think of every lot as a rocket lot, but the TPT is not going to be the 9 days that Semi was talking about... Because the equipment would not be so highly tuned and people trained on it as they are later in the development cycle.
Right, I don't want to give anyone a mis-impression. 9 days was a record, but it was also a "Rush Effort", because a prominent presentation was coming up. Multi-lots were started, in case of tool breakage, In each step of the process, the best performing tool was used, and the tool at the next step was held open waiting for the lot to arrive. The lots were hand carried by specific owners, no defect inspection or critical dimension measurement was done at any layer, and each tool had the process engineer, and the best equipment technician, standing in front of the tool while the lot ran in case anything went wrong. It was a 1 time effort, not a normal Hot Lot run, and not exactly what you would call Normal Operations.
BTW, as I recall, the lots yielded well enough, if they weren't enginering lots...... to otherwise sell as product
I'll accept the nit pick... it is good data.
Remember that AMD is doing 9 metal layers which does add some to the TPT. I did not want to muddy up the explaination.....
That's true, I forgot, additional metal layers would add throuhput time, so that does fit better. My estimate was for 6-8 layer metal. A case of go with what you know I guess
BTW, The last time I was in a fab was Fab 7 in Abq, around 1984. I was playing yield manager at the time. I am sure things have changed quite a bit since then
--Alan
Ah Ha.... I thought I detected a deeper process knowledge then I usually encounter around these parts, or that could be obtained just from web reading. Makes sense now. Whew, 84 huh....? That's almost ancient history. I was still an equipment tech in wafer sort/final test, way back then. I bet you still remember them manually dipping wafers in wet benches, and lighting diffusion furnaces with bic lighters, eh?
Semi
The times correspond very well with my data for volume production.
Just curious, are rocket-lots out of fashion for engineering wafers nowadays?
K.
Hot Lots are determined by need, and available capacity, but not out of fashion in engineering, afaik
BTW, afaik, the current record fab throughput on one such lot is..... 9 days (Microprocessor/130nm)
The real killer is that the time from a wafer started to results is over 4 months... it takes that long to know if you have something like a plumbing line that might be too long. Of course once you know you have a problem you have to figure out what it is and how to fix it... then rerun the whole thing which takes another 4 months. The problem may not be that hard, and it probably does not take the best and the brightest process engineers to get the job done... but it will take time.
--Alan
Please forgive the nit pick, since so far your manufacturing information appears to be reasonably accurate, and I'm not sure when the last time you manufactured wafers was, but FYI, Metal-1 etest, which provides transistor functionality, and switching speed data, is available ~ 5-6 weeks after wafer start, which would give significant process feedback. Also, world class manufacturing time to sort is now ~ 8-10 weeks. Add 2 additional weeks for wafer sort, packaging, burn in and final test, and finished products are available ~ 10-12 weeks after wafers start. ~ 1 month less then cited.
Maybe Intel's 90 nm process is healthy after all. :-P
There is nothing......
Sigh...... OK, I'll give you guys a break.
Acer Centrino Gaming Laptop:
http://www.pcmag.com/article2/0,1759,1631980,00.asp
What suprised me here is that the 1.8GHZ Dothan based laptop beat a Pentium 3.2GHZ pretty consistently! Gaming included.
Ya know, I think gaming is growing significantly on laptops, now that the Screen Sizes, Graphics, and CPU power can support games. I have a Centrino Laptop, and I actually like it's gaming capability. My "Mucho Mucho Tropico" game, runs fabulously. Yeah, I know, it's an old game, but I wasn't sure it would run well, because once you get, oh say 30-40 years into the simulation, it takes quite a bit of horsepower to keep it running at max resolution, without framerate dropouts. It runs on my laptop, as smooth as a baby's bottom
Merced was in development for over 6 years.
So, in that case then, intuitively, the 5 year Nacona plan claim doesn't make sense. Consider..... a brand new chip core, Merced, from scratch took 6 years. Nacona is not brand new chip from scratch. It's Prescott core, with EM64T added. Therefore, I think, a more applicable comparison would be, how long was Opteron in development, and how long would it have taken with intel's resources? If it took previous intel chip designers 6 years for a brand new core Merced, and I'm wrong about Nacona being reactive, and you are correct that it currently takes 5 years for intel to design Nacona "extensions" with core already completed, then that doesn't say too much for the skills of the current intel chip designers, now does it
BTW, the 64 bit features in Nocona have been in planning
and development for about 5 years. Do you think Intel
"back-stabbed" its IPF partner HP by offering its own
64 bit competitor?
A 64 bit competitor to what, Itanium? I don't think HP gives a rats arse if intel is producing Nacona and Itanium, and competing with itself. HP urged intel to go the Itanium route to replace HP's own offerings, not to compete with anything HP had.
Also, I don't think Nacona has been in development for 5 years, if it was, it would be better then it is. IMO, Nacona is only the result of a failure of Itanium to come to planned frutation, and pressure from AMD, and what the market wants now. It is a result of intel admitting they initially made the wrong choice by not first going with extended 32/64, like they did when intel went from 16/32 bit. Had intel "planned" correctly, they would have developed a kick arse Nacona FIRST, BEFORE AMD, and would only now be introducing Itanium, just in time for WIN64. No, I think that Nacona is a completly reactive response, not the result of any proactive "planning" at all.
Nah, HP can't compete with Dell in pricing and efficiency
but it also has to fend off second and third tier players
who were competing on features with Opteron systems.
HP is just doing what it has to do. Obviously HP has to
get its own house back in order on several fronts.
Yeah, sure they did, but as far as what they "had to do", IMO, HP's excuses are like arseholes, everybody's got one, and they all stink. The way I heard the story, intel went the Itanium route initially instead of the extended 32/64 route, partially at the urging of HP. So don't expect any sympaty for HP from me, despite my agreement that of course they are doing "what they had to do". Many backstabbings in history have been justified as such, and that reasoning doesn't make me at all sympathetic to those backstabbers either
Here's some more good Intel related news:
http://www1.us.dell.com/content/topics/global.aspx/corp/pressoffice/en/2004/2004_08_12_rr_000?c=us&a....
Ha...... Gee, that news, must have really disappointed the Droids. After blaming HPQ's disappointing results on intel, they must certainly be in a tizzy now, since it appears that an all intel vendor meets expectations. Somehow though, I'm finding it difficult to generate any sympaty for HPQ. Maybe HPQ should have stuck with a winner, instead of trying to stab them in the back
Shelton: Covington Reincarnated?
http://www.overclockers.com/articles1081/
The Inquirer reports that Intel is introducing a processor called Shelton in a few Asian countries which looks like the great-grandchild of Covington.
How much can this chip possibly cost? The original Covington used a 250nm process technology and was 130 sq. mm. If this were simply a process shrink, a 90nm Covington would be less than 20 sq.mm, or about a quarter the size of a current Athlon Thorougbred XP chip.
Manufacturing costs per chip for such a chip would be less than $5, might be more like $3. This is potentially one cheap chip; Intel could sell this chip to OEMs for $10-15 in bulk.
Match it up with old, shrunk down socket 370 technology, and you have a platform that will make Sempron look expensive.
What I want to know, is why Ed keeps stealing my posts
http://www.investorshub.com/boards/read_msg.asp?message_id=3792098
If this is true, it's the death knell for Intel, isn't it? How could they possibly sell systems at this price? Even if they sold more systems, this would be like any other "China priced" market. There comes a time where there are only very low margins. This would not fit well with Intel's operational environment of driving geometries and massive volumes and more fabs...
Smooth
First, because, for the recently reported chip (if true), intel most likely, reused a previous design, shrunk it to 90nm and sliced off the cache. Since the logic was already designed, and layed out, there would be little development cost there, except for straight shrink, and cutting out the cache. Second, since the individual die would now be smaller without the cache, you can fit more die on a wafer, reducing the individual die cost. Third, it's on 90nm and 12 inch wafers, so again, more die available, and again, the manufacturing costs per die are reduced further.
No, I don't think this is a "death knell" for intel. Not at all. It does however occur to me that it could be the beginning of a death knell for "some other companies" recently introduced product.
Semi, I don't agree with your analysis of Intel's new Celeronized Celeron. They had to have planned this product long before realizing a couple weeks ago that they had overcapacity.
*** Why? First off, I don't think that intel realized just "a couple of weeks ago that they had overcapacity". Orders for semiconductors are taken for a specific delivery date months down the road. Intel should have discovered the improved yields at MT1 etest. It is not difficult to extrapolate End Of Line yields, from the Metal1 etest data, which is done approximately mid-line, so intel would have known quite awhile ago that orders vs. yields were not going to match up.
Also, Since intel has it's own Internal Mask Operations, and the design was already on the IMO CAD Stations, it wouldn't be too difficult to shrink the design and slice off the cache. You would be surprised at how quickly a straight shrink, without any optimizations, can be done. Also, you do not need to have EVERY Layer Mask available at the onset. Metal Masks for example wouldn't be needed for ~ an additional 6 weeks.
I think Shelton, or whatever it's called, is simply a way to penetrate the most price conscious underdeveloped markets. It ought to be very easy to sell up most buyers to a regular Celeron when this chip has no cache and clocks at 1GHz.
*** Right, but if that's true, then where did they get the design from? At the low selling prices necessary to move these chips, you would most likely NOT recoup the development costs necessary to develop, layout, and produce a new design. It's much smarter to reuse an old design, and shrink it. Of course, intel doesn't seem to have been doing the smart thing the past couple of years, so maybe you're right. Actually, I'm not saying I'm right either, I don't know if intel did what I said, it's just what I would have done.
90nm ramp!
I was surprised by a visit to best buy yesterday. Every desktop except one was a prescott! All the celeron machines were 3xx series, and many of the Pentiums were the new 5xx series. There was one 2.8Ghz northwood system, as the lone 130nm product. I checked out the circuit city web site, and they are in the same position with only a single northwood system left on the product list.
It seems Intel has succeeded in converting the entire product line to 90nm prior to AMD releasing any 90nm products.
--Alan
Cool. Yup, it seems the 90nm yields are much better then intel expected. Guess those Prescott power issues really are a design issue, not a process issue. So, remind me......... Who was it in the past that kept saying on these boards that "There is nothing wrong with intel's 90nm process"?
Must have been some smart guy
Intel would not be producing new Celeron 300's would they? Wouldn't this be a sign of a problem with the production run? Was it a test to see the effect of 90nm on an old 300?
IDK, just curious.
I don't think it's a sign of any problems on 90nm. on the contrary, I think 90nm yields are better then expected, so there's just too much 90nm capacity, and not enough Prescott sales. Clearly, intel had planned the 90nm ramp for worse yields, and better sales numbers then have materialized. Their comments about 90nm inventory levels, seems to justify that.
In any case, my guess is, that if intel is using an old celeron design on 90nm, then most, if not all of the Litho Masks would need to be redone for a straight shrink to the smaller geometry. This could also allow some additional individual layer layout improvements. I have no clue if that was done, or if intel decided to economize, and just make the new masks as a straight 90nm shrink. Since they seem to not be including any cache, I would guess they are going the economical route, and running some sort of limited pilot runs, to see if the chip will even sell enough to soak up any temporary additional 90nm capacity, and give a return on the investment of making additional masks. If other 90nm sales pick up, expect these chips to disappear into the mist. JMO.
Cashless Intel Shelton takes on AMD Sempron
http://www.theinquirer.net/?article=17790
A VIETNAMESE web site said that Intel is introducing a chip called Shelton in Vietnam and in two other Asian countries.
But although its codename may be new, it appears to be a cut down Celeron from the past, clocking at 1GHz, using 90 nanometre process technology and with no, that's right no, level two cache.
*** So, I think this is a good idea. It has already been reported that the inventory buildup was from underestimating 90nm yields, and if the yields are good on 90nm and that capacity is available, why not put it to good use?
Employees at Intel stuff school-supply backpacks
http://www.azcentral.com/arizonarepublic/gilbert/articles/0809intel09Z6.html
Lars Jacoby
The Arizona Republic
Aug. 9, 2004 12:00 AM
The 600-plus students at Lowell Elementary are headed back to school with a backpack filled with school supplies, courtesy of Intel Corp. employees. But there's more to this back-to-school drive.
It kicks off a two-year partnership of Lowell, a science and math magnet school in central Phoenix, Intel's Chandler plant and Wells Fargo Bank. Plans also call for a $50,000 computer lab, computer and science clubs, new microscopes and a Big Brothers-Big Sisters program.
apparently intel's integrated graphics is doing well enough to be blamed by nvda for their poor latest quarterly results in the midrange. they also blamed the grantsdale recall for stalling their higher end stuff as well.
the relevance to intel is that if grantsdale integrated graphics is doing better than expected then it will be a fine thing to fill those 130nm fabs with.
gb
Don't you know? Every company that has a bad quarter, and has anything remotely to do with intel, will blame intel for their bad quarter? I heard the Janitorial service at intel had a bad financial quarter, and now they're saying it's intel's fault, because intel didn't dirty their bathrooms enough.
Intel Developer Forum Returns to San Francisco, Sept. 7-9
http://intel.com/pressroom/archive/releases/20040720alert.htm
When: Sept. 7-9, 2004
Where: Moscone Center South, San Francisco
What: Intel is opening up new worlds of technology at the Intel Developer Forum (IDF) Systems Conference, where attendees will find out what the impact will be on their projects and careers. IDF offers a fully immersive conference experience by bringing together technology leaders and experts for a program built upon training, networking and foresight.
Intel to introduce dual-core processors ahead of schedule
http://www.digitimes.com/news/a20040804PR206.html
Charles Chou, Taipei; Steve Shen, DigiTimes.com [Wednesday 4 August 2004]
Intel plans to unveil a dual-core processor, codenamed Smithfield, in mid-2005 instead of sometime in 2006, as originally planned, according to sources at Taiwan motherboard makers.
Tyan Intel server boards are little beauties
http://www.theinquirer.net/?article=17620
came out with Lindenhurst products today, and most were simply more of the same, only with longer press releases. Tyan came out with the usual slew of boards, but did at least one that really caught my attention, and it could be a very good thing.....
HP introduces 64-bit Prescott desktop
It calls it a workstation, but hey
http://www.theinquirer.net/?article=17608
By Mike Magee: Tuesday 03 August 2004, 09:07
TIN FIRM Hewlett Packard has started selling PCs which use 64-bit microprocessors from Intel that support the EM64T instruction set.........