". . .delayed due to the desire to utilize at least some of these advanced processes?"
I think the emphasis may be off here while the sentiment is about right.
Clearly a simple shrink from 90nm to 65nm doesn't reap the kind of benefits that were seen, for instance, in the 180nm->130nm node transition. This is well documented throughout the industry in spite of the analysts refusal to shift from the geometry metric as a measure of a semi mftr's prowess.
Wei even said that the future process performance improvements will NOT come from finer geometries. Of course yield/wafer will always benefit from smaller chips. Wei comments are confirmed by the article at RWT where it talks about whick knobs can be turned to tweak a process and how the traditional ones don't work anymore.
In the past it has often been the case that AMD changed everything at once - something rather risky. This time AMD has the luxury of shifting to 300mm at just one fab while keeps the design constant and just tweaking the process. This is something I am MUCH happier about.
The change to a Dual Strain Liner with SiGe looks to be very good news. It sounds like AMD engineers found the right knob to turn - and Intel's didn't. If AMD can realize the transistor-level improvements at a chip level it promises to put them even further ahead in the areas that are important, that is performance/watt, somewhere where they already have established quite a reputation.
In short its not that AMD delayed the shift to 65nm but rather 65nm is not the answer to what AMD wants. SiGe DSL *IS* what it wants. When more chips are needed, late in 2006/2007 then AMD can shift to 65nm and do it at a more leisurely and measured pace.
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