Replies to post #37608 on Advanced Micro Devices Inc (AMD)

[wbmw]

fpg, Re: This dual-core architecture will be able to approach the 100% speedup ideal closer than a regular 2-way Opteron system, as the cores will be able to communicate with each other at full speed without going past the SRQ, whereas the latter system must traverse each chip's SRQ and HTT interface.

For data access local to the CPU, you would be correct, which would make a single CPU dual core system attractive versus a dual CPU SMP system. However, remote accesses will put twice as much traffic on the Hypertransport links due to the dual cores, so remote bandwidth per core will be reduced. A 4-way (dual CPU, dual CMP) may be a wash over a regular 4-way SMP system.

[j3pflynn]

fpg - What exactly do you take from it on how the 2 cores access the caches? Separate caches or unified? Seems to me a lot is left out of the diagram - maybe it's already been made obvious elsewhere, I don't recall.
Paul

Edit: Ops, stupid question - hadn't looked at the second diagram yet!

[petrsny]

fastpathguru,

Margins on future dual-core products should be very good. No question. That's from a hardware point of view. But what about OS and aps? Additional charges?