Advanced Micro Devices Inc (AMD)

[fastpathguru]

Seems to imply that a dual-core, 2x1M L2 Hammer will be just under 200mm^2.

That's not too bad! Margins on these will be awesome too.

This dual-core architecture will be able to approach the 100% speedup ideal closer than a regular 2-way Opteron system, as the cores will be able to communicate with each other at full speed without going past the SRQ, whereas the latter system must traverse each chip's SRQ and HTT interface.

In fact, I wouldn't be surprised to see a greater-than-2x speedup over a like single-core chip in certain applications, thanks to efficient access to twice the cache. (Accessing the "other" cache ought to be faster than going to memory.)

fpg