Replies to post #24191 on Advanced Micro Devices Inc (AMD)

[dougSF30]

Keep on reading, Jerry R. You'll get to another post soon enough.

BTW, I made no comments regarding hi-freq low-IPC vs. anything else. I just noted the ridiculous overreach of the claim, as stated. I notice your screed contains a lot of "tends", "not clearly evident", "roughly", and the like, which isn't surprising.

In addition, the claim itself is obviously too loose to be true. It doesn't even insist on any notion of optimality in the designs to be compared. So add 100 copies of the circuitry to one of the designs, and what happens?

Note the context as well. It would have been just as easy to write: "No one can design anything better than Intel can!"

Doug

[greg s]

Excellent tutorial, Jerry, excellent.

[HailMary]

In a lower frequency, higher IPC design, you will tend to have far more logic gates changing state simultaneously (i.e. higher switching capacitance) per logic pipestage. In a higher frequency, lower IPC design, you will tend to have far fewer logic gates changing state per pipestage.

Higher frequency, lower IPC designs tend to have more gates overall. There is more feedback logic, more duplicated logic, more wiring, etc, so by nature lower IPC designs are less power efficient.

Someone should go find out the transistor counts of each of the major cores. I think you'll find P4 and Prescott have a lot more transistors than Athlon and Athlon64 cores given the same size cache. This is more telling than these simplified statements.

There is more to it than that though. Not all transistors on a chip are created equal. These days individual transistors can be tweaked for speed or power. Proper device loading is also important. You can optimize the load on a transistor for max speed or low power, or some combination.

Throw in process, and you have a hugely complex equation. Architecture choices, design optimizations, process tweaking. Too many factors to boil it down into such a simple statement.