dougSF30 - There are so many things wrong with that argument that I don't know where to begin.
You won't have to, because your inflammatory remark demonstrates a lack of understanding of digital logic design.
chipguy - To execute an x86 instruction takes a certain amount of logic gate wiggling. Regardless of whether a given level of performance is obtained by wiggling many logic gates relatively slowly or fewer gates faster, the amount of power consumed won't vary greatly for a given process feature size and supply voltage.
Roughly calculated, dynamic power consumption is equal to the switching capacitance of the design, the frequency of operation, and the square of the voltage.
In a lower frequency, higher IPC design, you will tend to have far more logic gates changing state simultaneously (i.e. higher switching capacitance) per logic pipestage. In a higher frequency, lower IPC design, you will tend to have far fewer logic gates changing state per pipestage. As a result, there is a classic engineering tradeoff, with no superior choice that's clearly evident.
What's important to note is the voltage squared term in the power equation, which dominates. The voltage "allowed" by a given design is a function of the microarchitectural implementation and the characteristics of the process.
It's clear that you are predisposed to believe that whatever AMD implements is the "superior" solution, but if you had any meaningful knowledge of microprocessor design, you would realize that chipguy's comment is pretty accurate.
