Advanced Micro Devices Inc (AMD)

[HailMary]

In a lower frequency, higher IPC design, you will tend to have far more logic gates changing state simultaneously (i.e. higher switching capacitance) per logic pipestage. In a higher frequency, lower IPC design, you will tend to have far fewer logic gates changing state per pipestage.

Higher frequency, lower IPC designs tend to have more gates overall. There is more feedback logic, more duplicated logic, more wiring, etc, so by nature lower IPC designs are less power efficient.

Someone should go find out the transistor counts of each of the major cores. I think you'll find P4 and Prescott have a lot more transistors than Athlon and Athlon64 cores given the same size cache. This is more telling than these simplified statements.

There is more to it than that though. Not all transistors on a chip are created equal. These days individual transistors can be tweaked for speed or power. Proper device loading is also important. You can optimize the load on a transistor for max speed or low power, or some combination.

Throw in process, and you have a hugely complex equation. Architecture choices, design optimizations, process tweaking. Too many factors to boil it down into such a simple statement.