Replies to post #24177 on Advanced Micro Devices Inc (AMD)

[dougSF30]

There are so many things wrong with that argument that I don't know where to begin.

Doug

[UpNDown]

chipguy, on logic gates and speed

Regardless of whether a given level
of performance is obtained by wiggling many logic gates
relatively slowly or fewer gates faster, the amount of
power consumed won't vary greatly for a given process
feature size and supply voltage.

But wouldn't a longer pipeline imply more need for temporary storage, rename registers, etc.? Thus, a longer pipeline would need more logic gates, but with smaller per-cycle work units, allow higher frequencies? The higher frequencies would allow the undesirable effects of the longer pipeline on branch mispredictions or other fault to be compensated for (and more so) by higher frequency?

It seems the lower IPC/higher frequency route leads to more power usage -- more logic gates driven at a higher speed. Please explain where I'm wrong?

[HailMary]

To execute an x86 instruction takes a certain amount of
logic gate wiggling. Regardless of whether a given level
of performance is obtained by wiggling many logic gates
relatively slowly or fewer gates faster, the amount of
power consumed won't vary greatly for a given process
feature size and supply voltage.

I'm surprised by your post, chipguy. That is way oversimplified. Architectures themselves can be high or low power oriented based on their efficiency and amount of speculative execution they do. It is all about tradeoffs. You can add an architecture feature that might buy you 2% in benchmarks, but adds 5% in power consumption. The project planners have to decide what is more important. It is all about making wise choices early on.

Also - the physical design itself can be optimized for power. I would guess Intel has the upper hand here as they have lots of resources to throw at this.