Replies to post #45792 on Intel Corp (INTC)

[wbmw]

Re: Looks like processing variation is not well
controlled in AMD's 65 nm process. Sucks to be AMD
when it tries to ramp its naive quad cores with far more
logic transistor on-die. Pity it can't match up low and
high leakage devices in MCMs to reduce TDP variation
at the socket level. Oh well...

There are other interesting things as well. Notice how high they have to keep on ratcheting up the voltage in order to hit higher frequencies. They seem to need as high as 1.3V for 1.9GHz, 1.325V for 2.3GHz, and 1.35V for 2.5GHz. It looks like their BE-2000 series parts are lower voltage than this, which enables the 45W TDP, but they can only reach 2.1GHz today....

Moreover, their leakage seems to triple with only 200mV. That's a really thin window. Obviously, they can't reach their clock frequency targets at 1.1V, but leakage starts to explode above 1.3V. It's a catch-22! For their 3600+ chip, 65% of the TDP power comes from leakage! The 'Droids are disillusioned if they think that SOI has given AMD a free pass in this area.

And by the way, I agree that an MCM approach to quad core would have been better for them, because they could have mixed low leakage and high leakage parts. You have been saying this for a long time, but now you can point to some numbers.

Let's say you combined two of these cores to form a hypothetical quad core Brisbane. Based on the figures below, you might end up with a part with 33.2A current draw at 1.35V, and another one with 64.4A current draw at 1.3V. And unlike a quad core Brisbane, Barcelona will have even more of these power hungry transistors. How will AMD be able to release a 1.9GHz Barcelona (equivalent frequency to the 3600+) at 68W TDP and 2.1GHz Barcelona at 95W TDP with this kind of process variation? The yields will be terrible, and they'll be forced to throw out a good percentage of their parts.

Suddenly, all of AMD's roadmap problems are crystal clear to me....

I think it will be very interesting to see how long it will take AMD to solve these problems. Unless they completely overhaul their 65nm process, I can't see how they can to it. You can't modify the design to fix this. No amount of power management can fix the amount of leakage while active....