Intel Corp (INTC)

[chipguy]

Anyway, I thought people would find this interesting.

Nice spot. Looks like processing variation is not well
controlled in AMD's 65 nm process. Sucks to be AMD
when it tries to ramp its naive quad cores with far more
logic transistor on-die. Pity it can't match up low and
high leakage devices in MCMs to reduce TDP variation
at the socket level. Oh well...

BTW, another datasheet thing to be very wary of is the
junction temperature the vendor specs idle and sleep
power state current consumption. If it is unrealistically
low then they are misrepresenting power consumption
in some kinds of systems and/or under certain kinds
of operating conditions (e.g. regularly slipping in and
out of idle state based on the OS tick timer etc).

Remember, leakage current approximately doubles for
every 10 deg C rise in temp.

P.S. (to Chipguy) I posted your other response on SI.

Thanks. I noticed you had no trouble identifying the
idiot in question.