Replies to post #33522 on Intel Corp (INTC)

[ChipGeek]

I am quite clueless on the technical aspects of CSI. Does anybody know if CSI will somehow prevent Intel from easily creating these MCM dual-core modules once they transition over to this new bus topology? Will it be easier or harder to do this than it is with an FSB topology?

The reason I ask is this: It's no secret that Intel's first MCM dual-core chip, Smithfield, was a day late and a dollar short, and likely contributed to this bad rap that the MCM approach is now getting.

But when I look at the situation today and extrapolate out into the future, I see a very big competitive advantage to this approach. Less than 6 months after introducing a "native" dual-core chip, Intel will roll out a quad-core offering, months before AMD can.

Of course, AMD has a "native" quad-core chip in development, but so does Intel (at the 45nm node). AMD's will come out first in mid-late 2007, but when Intel's is released, can't they just slap two of 'em together and push the market ahead to 8-core right off the bat? Wouldn't this in effect be YEARS before AMD could do anything "native"?

My prediction: before this decade is out, we will have fully transitioned from a "GHz war" to a "core war", and will see AMD copy this MCM strategy just to keep up with Intel.

The one hangup to this is my complete lack of understanding of how CSI works, and whether an MCM module is feasible using CSI.